Principles of Secure Processor Architecture Design (Hardcover)

This book presents the different challenges of secure processor architecture design for architects working in industry who want to add security features to their designs as well as graduate students interested in research on architecture and hardware security. It educates readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, it presents numerous design suggestions, as well as discussing pitfalls and fallacies that designers should avoid. With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book gives readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered).

General

Imprint:	Morgan & Claypool Publishers
Country of origin:	United States
Series:	Synthesis Lectures on Computer Architecture
Release date:	October 2018
Authors:	Jakub Szefer
Series editors:	Margaret Martonosi
Dimensions:	235 x 191 x 17mm (L x W x T)
Format:	Hardcover
Pages:	173
ISBN-13:	978-1-68173-404-0
Categories:	Books > Computing & IT > General theory of computing > General Books > Computing & IT > Computer communications & networking > Network security Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN:	1-68173-404-4
Barcode:	9781681734040

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