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Books > Professional & Technical > Energy technology & engineering > Electrical engineering
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Low Power High Speed CMOS Multiplexer Design (Hardcover)
Loot Price: R3,982
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Low Power High Speed CMOS Multiplexer Design (Hardcover)
Expected to ship within 12 - 17 working days
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This book proposes the reversible logic Multiplexer and also
demarcates between reversible and irreversible logic Multiplexers.
For power reduction in future computing technologies, reversible
logic is a very productive approach of logic synthesis. The purpose
of this book is to reduce power and area of 2:1 MUX, 4:1 MUX and
reversible logic while maintaining the viable performance. The
diverse configurations are designed using different topologies of
2:1 MUX and 4:1 MUX such as CMOS based MUX, transmission gate and
pass transistor. The editors propose a new application of GDI
(Gate-Diffusion Input) circuits to Reversible logic multiplexer
with its Garbage input and output. The novel proposed design
technique will consume less power than the other conventional gate.
Reversible logic circuit has displayed less power dissipation in
recent years. Additionally, this GDI cell technique decreases the
power of the circuit, delay, Power-Delay Product (PDP) and it also
compacts the frequency. The device scaling is partial as the power
dissipations is more optimized in terms of delay, frequency jitter,
bandwidth power supply, frequency and duty cycle of the signal and
also establishes the noise of the circuit. In the reversible logic
design, the GDI is efficient in lower delay, low power and low
leakage current.
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