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Leakage Current and Ground Bounce Noise Aware MTCMOS Techniques (Paperback): Shashikant Sharma, Manisha Pattanaik, Balwinder Raj Leakage Current and Ground Bounce Noise Aware MTCMOS Techniques (Paperback)
Shashikant Sharma, Manisha Pattanaik, Balwinder Raj
R1,004 Discovery Miles 10 040 Ships in 10 - 15 working days

As technology is continuously scaling down leakage current is increasing exponentially. Contribution of leakage current is around 50% to the total operational power of digital circuits. With increasing demand of portable battery operated devices like cell phones, pagers and laptops, low power design has become important design style for future battery powered devices. This exponential increase in leakage power has made Multi-Threshold CMOS (MTCMOS) technique an attractive design choice for low power application. Conventional MTCMOS techniques for minimizing leakage current gives rise to ground bounce noise during mode transition which is also an important challenge and reduces the reliability of the circuit. In this work different multi-threshold CMOS techniques have been presented and compared which uses the concept of forward body biasing, diode connected MOS, ultra low power diode and signal stepping.Proposed designs has shown significant improvement in ground bounce noise and standby leakage current as compared to designs proposed in past.

Energy Efficient VLSI Design and Implementation on 28nm FPGA (Paperback): Bishwajeet Pandey, Manisha Pattanaik Energy Efficient VLSI Design and Implementation on 28nm FPGA (Paperback)
Bishwajeet Pandey, Manisha Pattanaik
R1,767 Discovery Miles 17 670 Ships in 10 - 15 working days

In the era of High Performance Energy Efficient Computing (HPEEC), the focus of research is again shifting for Eco-friendly design. Eco-Friendly design is a environment friendly design which has achieved energy efficiency in signicant amount. In this work, we applied 3 clock gating techniques (Latch Free, Latch Based, Flip-Flop Based) on 3 ALU(Synchronous, Asynchronous and Global Reset) to find the most energy efficient techniques out of 6 combination under consideration. Then, we try to get the benefit of 28nm technology in term of energy efficiency, which delivers twice the gate density of the 40nm process and also features a BRAM cell size shrink of 50 percent. Finally, we search for the most energy efficient IO Standard for latch free clock gated global reset ALU to design the most energy efficient ALU possible.

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