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This book provides a comprehensive presentation of the most
advanced research results and technological developments enabling
understanding, qualifying and mitigating the soft errors effect in
advanced electronics, including the fundamental physical mechanisms
of radiation induced soft errors, the various steps that lead to a
system failure, the modelling and simulation of soft error at
various levels (including physical, electrical, netlist, event
driven, RTL, and system level modelling and simulation), hardware
fault injection, accelerated radiation testing and natural
environment testing, soft error oriented test structures,
process-level, device-level, cell-level, circuit-level,
architectural-level, software level and system level soft error
mitigation techniques. The book contains a comprehensive
presentation of most recent advances on understanding, qualifying
and mitigating the soft error effect in advanced electronic
systems, presented by academia and industry experts in reliability,
fault tolerance, EDA, processor, SoC and system design, and in
particular, experts from industries that have faced the soft error
impact in terms of product reliability and related business issues
and were in the forefront of the countermeasures taken by these
companies at multiple levels in order to mitigate the soft error
effects at a cost acceptable for commercial products. In a fast
moving field, where the impact on ground level electronics is very
recent and its severity is steadily increasing at each new process
node, impacting one after another various industry sectors (as an
example, the Automotive Electronics Council comes to publish
qualification requirements on soft errors), research and technology
developments and industrial practices have evolve very fast,
outdating the most recent books edited at 2004.
Test functions (fault detection, diagnosis, error correction,
repair, etc.) that are applied concurrently while the system
continues its intended function are defined as on-line testing. In
its expanded scope, on-line testing includes the design of
concurrent error checking subsystems that can be themselves
self-checking, fail-safe systems that continue to function
correctly even after an error occurs, reliability monitoring, and
self-test and fault-tolerant designs. On-Line Testing for VLSI
contains a selected set of articles that discuss many of the modern
aspects of on-line testing as faced today. The contributions are
largely derived from recent IEEE International On-Line Testing
Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and
Dhiraj Pradhan organized the articles into six chapters. In the
first chapter the editors introduce a large number of approaches
with an expanded bibliography in which some references date back to
the sixties. On-Line Testing for VLSI is an edited volume of
original research comprising invited contributions by leading
researchers.
Test functions (fault detection, diagnosis, error correction,
repair, etc.) that are applied concurrently while the system
continues its intended function are defined as on-line testing. In
its expanded scope, on-line testing includes the design of
concurrent error checking subsystems that can be themselves
self-checking, fail-safe systems that continue to function
correctly even after an error occurs, reliability monitoring, and
self-test and fault-tolerant designs. On-Line Testing for VLSI
contains a selected set of articles that discuss many of the modern
aspects of on-line testing as faced today. The contributions are
largely derived from recent IEEE International On-Line Testing
Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and
Dhiraj Pradhan organized the articles into six chapters. In the
first chapter the editors introduce a large number of approaches
with an expanded bibliography in which some references date back to
the sixties. On-Line Testing for VLSI is an edited volume of
original research comprising invited contributions by leading
researchers.
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