The molecular genetics of the cholinergic system including both muscarinic and nicotinic acetylcholine receptors, cholinesterases, acetylcholine synthesis and release have provided significant insights into potential targeting for pharmacological intervention. Cholinergic drugs are being used or evaluated for the treatment of diseases. Thus, this volume aims to broaden our understanding of the current state of cholinergic mechanisms to enable implementation of novel approaches for the development of more effective treatments.

The molecular genetics of the cholinergic system including both muscarinic and nicotinic acetylcholine receptors, cholinesterases, acetylcholine synthesis and release have provided significant insights into potential targeting for pharmacological intervention. Cholinergic drugs are being used or evaluated for the treatment of diseases. Thus, this volume aims to broaden our understanding of the current state of cholinergic mechanisms to enable implementation of novel approaches for the development of more effective treatments.

Designing reliable and optimal systems is one of the key challenges in contemporary electronics. This book provides novel insights into designing reliable systems with optimal configurations using Genetic Algorithms (GAs). GAs are highly customized processes, which work with large amounts of data and simple operators to yield optimal solutions to difficult problems. This book uses abstractions at the transistor, gate and systems level to demonstrate the heuristics and challenges in the design process. The book propounds a novel technique for evolving transistor net lists directly from truth table descriptions of arbitrary digital circuits, a gate-less custom VLSI design approach. It also explores the application of GAs in finding vector pairs that cause the peak power dissipation in circuits. In a third system, the design of FIR filters with an arbitrary frequency response is demonstrated with a custom GA. Finally a fourth optimization problem outlines the design methodology of a SEU tolerant Distributed RAM using Configurable Logic Blocks (CLBs) on FPGAs incorporating unused CLB BlockRAMs for high speed On-Chip memories and SEU resistant Tri-State Buffers (BUFTs) for ECC.