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Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.): Kothanda Umamageswaran, Sheetanshu L.... Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.)
Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
R2,746 Discovery Miles 27 460
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Ships in 18 - 22 working days

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback, Softcover reprint of the original 1st ed. 1999):... Formal Semantics and Proof Techniques for Optimizing VHDL Models (Paperback, Softcover reprint of the original 1st ed. 1999)
Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
R2,623 Discovery Miles 26 230
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Ships in 18 - 22 working days

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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