Synthesizable VHDL Design for FPGAs (Paperback, Softcover reprint of the original 1st ed. 2014)

The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Release date:	August 2016
First published:	2014
Authors:	Eduardo Augusto Bezerra • Djones Vinicius Lettnin
Dimensions:	235 x 155 x 9mm (L x W x T)
Format:	Paperback
Pages:	157
Edition:	Softcover reprint of the original 1st ed. 2014
ISBN-13:	978-3-319-37733-9
Categories:	Books > Computing & IT > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Promotions
LSN:	3-319-37733-7
Barcode:	9783319377339

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