Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
|
Buy Now
Low-Voltage CMOS Log Companding Analog Design (Hardcover, 2003 ed.)
Loot Price: R3,137
Discovery Miles 31 370
|
|
Low-Voltage CMOS Log Companding Analog Design (Hardcover, 2003 ed.)
Series: The Springer International Series in Engineering and Computer Science, 733
Expected to ship within 10 - 15 working days
|
Low-Voltage CMOS Log Companding Analog Design presents in detail
state-of-the-art analog circuit techniques for the very low-voltage
and low-power design of systems-on-chip in CMOS technologies. The
proposed strategy is mainly based on two bases: the Instantaneous
Log Companding Theory, and the MOSFET operating in the subthreshold
region. The former allows inner compression of the voltage
dynamic-range for very low-voltage operation, while the latter is
compatible with CMOS technologies and suitable for low-power
circuits. The required background on the specific modeling of the
MOS transistor for Companding is supplied at the beginning.
Following this general approach, a complete set of CMOS basic
building blocks is proposed and analyzed for a wide variety of
analog signal processing. In particular, the covered areas include:
amplification and AGC, arbitrary filtering, PTAT generation, and
pulse duration modulation (PDM). For each topic, several case
studies are considered to illustrate the design methodology. Also,
integrated examples in 1.2um and 0.35um CMOS technologies are
reported to verify the good agreement between design equations and
experimental data. The resulting analog circuit topologies exhibit
very low-voltage (i.e. 1V) and low-power (few tenths of uA)
capabilities. Apart from these specific design examples, a real
industrial application in the field of hearing aids is also
presented as the main demonstrator of all the proposed basic
building blocks. This system-on-chip exhibits true 1V operation,
high flexibility through digital programmability and very low-power
consumption (about 300uA including the Class-D amplifier). As a
result, the reported ASIC can meet the specifications of a complete
family of common hearing aid models. In conclusion, this book is
addressed to both industry ASIC designers who can apply its
contents to the synthesis of very low-power systems-on-chip in
standard CMOS technologies, as well as to the teachers of modern
circuit design in electronic engineering.
General
Is the information for this product incomplete, wrong or inappropriate?
Let us know about it.
Does this product have an incorrect or missing image?
Send us a new image.
Is this product missing categories?
Add more categories.
Review This Product
No reviews yet - be the first to create one!
|
|
Email address subscribed successfully.
A activation email has been sent to you.
Please click the link in that email to activate your subscription.