Pipelined Multiprocessor System-on-Chip for Multimedia (Paperback, Softcover reprint of the original 1st ed. 2014)

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Release date:	August 2016
First published:	2014
Authors:	Haris Javaid • Sri Parameswaran
Dimensions:	235 x 155 x 10mm (L x W x T)
Format:	Paperback
Pages:	169
Edition:	Softcover reprint of the original 1st ed. 2014
ISBN-13:	978-3-319-34711-0
Categories:	Books > Computing & IT > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Promotions
LSN:	3-319-34711-X
Barcode:	9783319347110

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