Leakage in Nanometer CMOS Technologies (Hardcover, 2006 ed.)

The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction. Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles. The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions. Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions. mitigate increases in the leakage components as technology scales.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Series:	Integrated Circuits and Systems
Release date:	November 2005
First published:	2006
Editors:	Siva G. Narendra • Anantha P. Chandrakasan
Dimensions:	235 x 156 x 19mm (L x W x T)
Format:	Hardcover
Pages:	308
Edition:	2006 ed.
ISBN-13:	978-0-387-25737-2
Categories:	Books > Professional & Technical > Electronics & communications engineering > General Promotions
LSN:	0-387-25737-3
Barcode:	9780387257372

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