In the deep sub-micron regime, the power consumption has become one
of the most important issues for competitive design of digital
circuits. Due to dramatically increasing leakage currents, the
power consumption does not take advantage of technology scaling as
before. State-of-art power reduction techniques like the use of
multiple supply and threshold voltages, transistor stack forcing
and power gating are discussed with respect to implementation and
power saving capability. Focus is given especially on technology
dependencies, process variations and technology scaling. Design and
implementation issues are discussed with respect to the trade-off
between power reduction, performance degradation, and system level
constraints. A complete top-down design flow is demonstrated for
power gating techniques introducing new design methodologies for
the switch sizing task and circuit blocks for data-retention and
block activation.
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