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The simplest method of transferring data through the inputs or
outputs of a silicon chip is to directly connect each bit of the
datapath from one chip to the next chip. Once upon a time this was
an acceptable approach. However, one aspect (and perhaps the only
aspect) of chip design which has not changed during the career of
the authors is Moore's Law, which has dictated substantial
increases in the number of circuits that can be manufactured on a
chip. The pin densities of chip packaging technologies have not
increased at the same pace as has silicon density, and this has led
to a prevalence of High Speed Serdes (HSS) devices as an inherent
part of almost any chip design. HSS devices are the dominant form
of input/output for many (if not most) high-integration chips,
moving serial data between chips at speeds up to 10 Gbps and
beyond. Chip designers with a background in digital logic design
tend to view HSS devices as simply complex digital input/output
cells. This view ignores the complexity associated with serially
moving billions of bits of data per second. At these data rates,
the assumptions associated with digital signals break down and
analog factors demand consideration. The chip designer who
oversimplifies the problem does so at his or her own peril.
The simplest method of transferring data through the inputs or
outputs of a silicon chip is to directly connect each bit of the
datapath from one chip to the next chip. Once upon a time this was
an acceptable approach. However, one aspect (and perhaps the only
aspect) of chip design which has not changed during the career of
the authors is Moore's Law, which has dictated substantial
increases in the number of circuits that can be manufactured on a
chip. The pin densities of chip packaging technologies have not
increased at the same pace as has silicon density, and this has led
to a prevalence of High Speed Serdes (HSS) devices as an inherent
part of almost any chip design. HSS devices are the dominant form
of input/output for many (if not most) high-integration chips,
moving serial data between chips at speeds up to 10 Gbps and
beyond. Chip designers with a background in digital logic design
tend to view HSS devices as simply complex digital input/output
cells. This view ignores the complexity associated with serially
moving billions of bits of data per second. At these data rates,
the assumptions associated with digital signals break down and
analog factors demand consideration. The chip designer who
oversimplifies the problem does so at his or her own peril.
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