Many small and medium scale businesses cannot afford to procure expensive cybersecurity tools. In many cases, even after procurement, lack of a workforce with knowledge of the standard architecture of enterprise security, tools are often used ineffectively. The Editors have developed multiple projects which can help in developing cybersecurity solution architectures and the use of the right tools from the open-source software domain. This book has 8 chapters describing these projects in detail with recipes on how to use open-source tooling to obtain standard cyber defense and the ability to do self-penetration testing and vulnerability assessment. This book also demonstrates work related to malware analysis using machine learning and implementation of honeypots, network Intrusion Detection Systems in a security operation center environment. It is essential reading for cybersecurity professionals and advanced students.

This book of 'directions' focuses on cyber security research, education and training in India, and work in this domain within the Indian Institute of Technology Kanpur. IIT Kanpur's Computer Science and Engineering Department established an 'Interdisciplinary Center for Cyber Security and Cyber Defense of Critical Infrastructures (C3I Center)' in 2016 with funding from the Science and Engineering Research Board (SERB), and other funding agencies. The work at the center focuses on smart grid security, manufacturing and other industrial control system security; network, web and data security; cryptography, and penetration techniques. The founders are involved with various Indian government agencies including the Reserve Bank of India, National Critical Information Infrastructure Protection Center, UIDAI, CCTNS under home ministry, Ministry of IT and Electronics, and Department of Science & Technology. The center also testifies to the parliamentary standing committee on cyber security, and has been working with the National Cyber Security Coordinator's office in India. Providing glimpses of the work done at IIT Kanpur, and including perspectives from other Indian institutes where work on cyber security is starting to take shape, the book is a valuable resource for researchers and professionals, as well as educationists and policymakers.

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Human lives are getting increasingly entangled with technology, especially comp- ing and electronics. At each step we take, especially in a developing world, we are dependent on various gadgets such as cell phones, handheld PDAs, netbooks, me- cal prosthetic devices, and medical measurement devices (e.g., blood pressure m- itors, glucometers). Two important design constraints for such consumer electronics are their form factor and battery life. This translates to the requirements of reduction in the die area and reduced power consumption for the semiconductor chips that go inside these gadgets. Performance is also important, as increasingly sophisticated applications run on these devices, and many of them require fast response time. The form factor of such electronics goods depends not only on the overall area of the chips inside them but also on the packaging, which depends on thermal ch- acteristics. Thermal characteristics in turn depend on peak power signature of the chips. As a result, while the overall energy usage reduction increases battery life, peak power reduction in?uences the form factor. One more important aspect of these electronic equipments is that every 6 months or so, a newer feature needs to be added to keep ahead of the market competition, and hence new designs have to be completed with these new features, better form factor, battery life, and performance every few months. This extreme pressure on the time to market is another force that drives the innovations in design automation of semiconductor chips.

Perhaps nothing characterizes the inherent heterogeneity in embedded sys tems than the ability to choose between hardware and software implementations of a given system function. Indeed, most embedded systems at their core repre sent a careful division and design of hardware and software parts of the system To do this task effectively, models and methods are necessary functionality. to capture application behavior, needs and system implementation constraints. Formal modeling can be valuable in addressing these tasks. As with most engineering domains, co-design practice defines the state of the it seeks to add new capabilities in system conceptualization, mod art, though eling, optimization and implementation. These advances -particularly those related to synthesis and verification tasks -direct1y depend upon formal under standing of system behavior and performance measures. Current practice in system modeling relies upon exploiting high-level programming frameworks, such as SystemC, EstereI, to capture design at increasingly higher levels of ab straction and attempts to reduce the system implementation task. While raising the abstraction levels for design and verification tasks, to be really useful, these approaches must also provide for reuse, adaptation of the existing intellectual property (IP) blocks."

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

One of the grand challenges in the nano-scopic computing era is guarantees of robustness. Robust computing system design is confronted with quantum physical, probabilistic, and even biological phenomena, and guaranteeing high reliability is much more difficult than ever before. Scaling devices down to the level of single electron operation will bring forth new challenges due to probabilistic effects and uncertainty in guaranteeing 'zero-one' based computing. Minuscule devices imply billions of devices on a single chip, which may help mitigate the challenge of uncertainty by replication and redundancy. However, such device densities will create a design and validation nightmare with the shear scale.
The questions that confront computer engineers regarding the current status of nanocomputing material and the reliability of systems built from such miniscule devices, are difficult to articulate and answer. We have found a lack of resources in the confines of a single volume that at least partially attempts to answer these questions.
We believe that this volume contains a large amount of research material as well as new ideas that will be very useful for some one starting research in the arena of nanocomputing, not at the device level, but the problems one would face at system level design and validation when nanoscopic physicality will be present at the device level.

Fundamental Problems in Computing is in honor of Professor Daniel J. Rosenkrantz, a distinguished researcher in Computer Science. Professor Rosenkrantz has made seminal contributions to many subareas of Computer Science including formal languages and compilers, automata theory, algorithms, database systems, very large scale integrated systems, fault-tolerant computing and discrete dynamical systems. For many years, Professor Rosenkrantz served as the Editor-in-Chief of the Journal of the Association for Computing Machinery (JACM), a very prestigious archival journal in Computer Science. His contributions to Computer Science have earned him many awards including the Fellowship from ACM and the ACM SIGMOD Contributions Award.

ESL or "Electronic System Level" is a buzz word these days, in the electronic design automation (EDA) industry, in design houses, and in the academia. Even though numerous trade magazine articles have been written, quite a few books have been published that have attempted to de?ne ESL, it is still not clear what exactly it entails. However, what seems clear to every one is that the "Register Transfer Level" (RTL) languages are not adequate any more to be the design entry point for today's and tomorrow's complex electronic system design. There are multiple reasons for such thoughts. First, the c- tinued progression of the miniaturization of the silicon technology has led to the ability of putting almost a billion transistors on a single chip. Second, applications are becoming more and more complex, and integrated with c- munication, control, ubiquitous and pervasive computing, and hence the need for ever faster, ever more reliable, and more robust electronic systems is pu- ing designers towards a productivity demand that is not sustainable without a fundamental change in the design methodologies. Also, the hardware and software functionalities are getting interchangeable and ability to model and design both in the same manner is gaining importance. Given this context, we assume that any methodology that allows us to model an entire electronic system from a system perspective, rather than just hardware with discrete-event or cycle based semantics is an ESL method- ogy of some kind.

Embedded software is ubiquitous today. There are millions of lines of embedded code in smart phones, and even more in systems responsible for automotive control, avionics control, weapons control and space missions. Some of these are safety-critical systems whose correctness, timely response, and reliability are of paramount importance. These requirement pose new challenges to system designers. This necessitates that a proper design science, based on "constructive correctness" be developed. Correct-by-construction design and synthesis of embedded software is done in a way so that post-development verification is minimized, and correct operation of embedded systems is maximized. This book presents the state of the art in the design of safety-critical, embedded software. It introduced readers to three major approaches to specification driven, embedded software synthesis/construction: synchronous programming based approaches, models of computation based approaches, and an approach based on concurrent programming with a co-design focused language. It is an invaluable reference for practitioners and researchers concerned with improving the product development life-cycle.

Human lives are getting increasingly entangled with technology, especially comp- ing and electronics. At each step we take, especially in a developing world, we are dependent on various gadgets such as cell phones, handheld PDAs, netbooks, me- cal prosthetic devices, and medical measurement devices (e.g., blood pressure m- itors, glucometers). Two important design constraints for such consumer electronics are their form factor and battery life. This translates to the requirements of reduction in the die area and reduced power consumption for the semiconductor chips that go inside these gadgets. Performance is also important, as increasingly sophisticated applications run on these devices, and many of them require fast response time. The form factor of such electronics goods depends not only on the overall area of the chips inside them but also on the packaging, which depends on thermal ch- acteristics. Thermal characteristics in turn depend on peak power signature of the chips. As a result, while the overall energy usage reduction increases battery life, peak power reduction in?uences the form factor. One more important aspect of these electronic equipments is that every 6 months or so, a newer feature needs to be added to keep ahead of the market competition, and hence new designs have to be completed with these new features, better form factor, battery life, and performance every few months. This extreme pressure on the time to market is another force that drives the innovations in design automation of semiconductor chips.

SystemC Kernel Extensions for Heterogeneous System Modeling is a result of an almost two year endeavour on our part to understand how SystemC can be made useful for system level modeling at higher levels of abstraction. Making it a truly heterogeneous modeling language and platform, for hardware/software co-design as well as complex embedded hardware designs has been our focus in the work reported in this book.

Fundamental Problems in Computing is in honor of Professor Daniel J. Rosenkrantz, a distinguished researcher in Computer Science. Professor Rosenkrantz has made seminal contributions to many subareas of Computer Science including formal languages and compilers, automata theory, algorithms, database systems, very large scale integrated systems, fault-tolerant computing and discrete dynamical systems. For many years, Professor Rosenkrantz served as the Editor-in-Chief of the Journal of the Association for Computing Machinery (JACM), a very prestigious archival journal in Computer Science. His contributions to Computer Science have earned him many awards including the Fellowship from ACM and the ACM SIGMOD Contributions Award.

ESL or "Electronic System Level" is a buzz word these days, in the electronic design automation (EDA) industry, in design houses, and in the academia. Even though numerous trade magazine articles have been written, quite a few books have been published that have attempted to de?ne ESL, it is still not clear what exactly it entails. However, what seems clear to every one is that the "Register Transfer Level" (RTL) languages are not adequate any more to be the design entry point for today's and tomorrow's complex electronic system design. There are multiple reasons for such thoughts. First, the c- tinued progression of the miniaturization of the silicon technology has led to the ability of putting almost a billion transistors on a single chip. Second, applications are becoming more and more complex, and integrated with c- munication, control, ubiquitous and pervasive computing, and hence the need for ever faster, ever more reliable, and more robust electronic systems is pu- ing designers towards a productivity demand that is not sustainable without a fundamental change in the design methodologies. Also, the hardware and software functionalities are getting interchangeable and ability to model and design both in the same manner is gaining importance. Given this context, we assume that any methodology that allows us to model an entire electronic system from a system perspective, rather than just hardware with discrete-event or cycle based semantics is an ESL method- ogy of some kind.

SystemC Kernel Extensions for Heterogeneous System Modeling is a result of an almost two year endeavour on our part to understand how SystemC can be made useful for system level modeling at higher levels of abstraction. Making it a truly heterogeneous modeling language and platform, for hardware/software co-design as well as complex embedded hardware designs has been our focus in the work reported in this book.

One of the grand challenges in the nano-scopic computing era is guarantees of robustness. Robust computing system design is confronted with quantum physical, probabilistic, and even biological phenomena, and guaranteeing high reliability is much more difficult than ever before. Scaling devices down to the level of single electron operation will bring forth new challenges due to probabilistic effects and uncertainty in guaranteeing 'zero-one' based computing. Minuscule devices imply billions of devices on a single chip, which may help mitigate the challenge of uncertainty by replication and redundancy. However, such device densities will create a design and validation nightmare with the shear scale.
The questions that confront computer engineers regarding the current status of nanocomputing material and the reliability of systems built from such miniscule devices, are difficult to articulate and answer. We have found a lack of resources in the confines of a single volume that at least partially attempts to answer these questions.
We believe that this volume contains a large amount of research material as well as new ideas that will be very useful for some one starting research in the arena of nanocomputing, not at the device level, but the problems one would face at system level design and validation when nanoscopic physicality will be present at the device level.