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Implementation of a Binary Floating Point Fused Multiply-Add Unit (Paperback) Loot Price: R1,221
Discovery Miles 12 210
Repayment Terms: R114 pm x 12*
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Implementation of a Binary Floating Point Fused Multiply-Add Unit (Paperback): Abdel Aziz Ibrahim Walaa, Aly Fahmy Hossam,...

Implementation of a Binary Floating Point Fused Multiply-Add Unit (Paperback)

Abdel Aziz Ibrahim Walaa, Aly Fahmy Hossam, Hussien Khalil Ahmed

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Loot Price R1,221 Discovery Miles 12 210 | Repayment Terms: R114 pm x 12*

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The fused multiply add (FMA) operation is very important in many scientific and engineering applications. It is a key feature of the floating-point unit (FPU), which greatly increases the floating-point performance and accuracy.Many approaches are developed on floating-point fused multiply add unit to decrease its latency.two of these approaches are implemented in the Verilog hardware description language. ModelSim10.0c is a used to compile Verilog codes and to simulate them.

General

Imprint: Lap Lambert Academic Publishing
Country of origin: United States
Release date: December 2012
First published: December 2012
Authors: Abdel Aziz Ibrahim Walaa • Aly Fahmy Hossam • Hussien Khalil Ahmed
Dimensions: 229 x 152 x 6mm (L x W x T)
Format: Paperback - Trade
Pages: 104
ISBN-13: 978-3-8465-4621-5
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > General
LSN: 3-8465-4621-6
Barcode: 9783846546215

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