Source-Synchronous Networks-On-Chip - Circuit and Architectural Interconnect Modeling (Hardcover, 2014 ed.)

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic."

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	November 2013
First published:	2014
Authors:	Ayan Mandal • Sunil P. Khatri • Rabi Mahapatra
Dimensions:	235 x 155 x 15mm (L x W x T)
Format:	Hardcover
Pages:	143
Edition:	2014 ed.
ISBN-13:	978-1-4614-9404-1
Categories:	Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN:	1-4614-9404-4
Barcode:	9781461494041

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