SVA: The Power of Assertions in SystemVerilog (Hardcover, 2nd ed. 2015)

This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012. System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Release date:	September 2014
First published:	2015
Authors:	Eduard Cerny • Surrendra Dudani • John Havlicek • Dmitry Korchemny
Dimensions:	235 x 155 x 38mm (L x W x T)
Format:	Hardcover
Pages:	590
Edition:	2nd ed. 2015
ISBN-13:	978-3-319-07138-1
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
LSN:	3-319-07138-6
Barcode:	9783319071381

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