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High-Level Synthesis for Real-Time Digital Signal Processing (Hardcover, 1993 ed.)
Loot Price: R4,326
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High-Level Synthesis for Real-Time Digital Signal Processing (Hardcover, 1993 ed.)
Series: The Springer International Series in Engineering and Computer Science, 216
Expected to ship within 12 - 17 working days
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High-Level Synthesis for Real-Time Digital Signal Processing is a
comprehensive reference work for researchers and practicing ASIC
design engineers. It focuses on methods for compiling complex, low
to medium throughput DSP system, and on the implementation of these
methods in the CATHEDRAL-II compiler. The emergence of independent
silicon foundries, the reduced price of silicon real estate and the
shortened processing turn-around time bring silicon technology
within reach of system houses. Even for low volumes, digital
systems on application-specific integrated circuits (ASICs) are
becoming an economically meaningful alternative for traditional
boards with analogue and digital commodity chips. ASICs cover the
application region where inefficiencies inherent to general-purpose
components cannot be tolerated. However, full-custom handcrafted
ASIC design is often not affordable in this competitive market.
Long design times, a high development cost for a low production
volume, the lack of silicon designers and the lack of suited design
facilities are inherent difficulties to manual full-custom chip
design. To overcome these drawbacks, complex systems have to be
integrated in ASICs much faster and without losing too much
efficiency in silicon area and operation speed compared to
handcrafted chips. The gap between system design and silicon design
can only be bridged by new design (CAD). The idea of a silicon
compiler, translating a behavioural system specification directly
into silicon, was born from the awareness that the ability to
fabricate chips is indeed outrunning the ability to design them. At
this moment, CAD is one order of magnitude behind schedule.
Conceptual CAD is the keyword to mastering the design complexity in
ASIC design and the topic of this book.
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