This book is designed both for FPGA users interested in
developing new, specific components - generally for reducing
execution times -and IP core designers interested in extending
their catalog of specific components. The main focus is circuit
synthesis and the discussion shows, for example, how a given
algorithm executing some complex function can be translated to a
synthesizable circuit description, as well as which are the best
choices the designer can make to reduce the circuit cost, latency,
or power consumption. This is not a book on algorithms. It is a
book that shows how to translate efficiently an algorithm to a
circuit, using techniques such as parallelism, pipeline, loop
unrolling, and others. Numerous examples of FPGA implementation are
described throughout this book and the circuits are modeled in
VHDL. Complete and synthesizable source files are available for
download."
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