Compilation Techniques for Reconfigurable Architectures (Hardcover, 2009 ed.)

The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	October 2008
First published:	2009
Authors:	Joao M.P. Cardoso • Pedro C. Diniz
Dimensions:	235 x 155 x 17mm (L x W x T)
Format:	Hardcover
Pages:	223
Edition:	2009 ed.
ISBN-13:	978-0-387-09670-4
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Electronic devices & materials > General Promotions
LSN:	0-387-09670-1
Barcode:	9780387096704

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