As Moore's Law and Dennard scaling trends have slowed, the
challenges of building high-performance computer architectures
while maintaining acceptable power efficiency levels have
heightened. Over the past ten years, architecture techniques for
power efficiency have shifted from primarily focusing on
module-level efficiencies, toward more holistic design styles based
on parallelism and heterogeneity. This work highlights and
synthesizes recent techniques and trends in power-efficient
computer architecture. Table of Contents: Introduction / Voltage
and Frequency Management / Heterogeneity and Specialization /
Communication and Memory Systems / Conclusions / Bibliography /
Authors' Biographies
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