Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip (Hardcover, 1st ed. 2018)

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Release date:	July 2017
First published:	2018
Authors:	Pascal Meinerzhagen • Adam Teman • Robert Giterman • Noa Edri • Andreas Burg • Alexander Fish
Dimensions:	235 x 155mm (L x W)
Format:	Hardcover
Pages:	146
Edition:	1st ed. 2018
ISBN-13:	978-3-319-60401-5
Categories:	Books > Computing & IT > Computer hardware & operating systems > Storage media & peripherals Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN:	3-319-60401-5
Barcode:	9783319604015

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