The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits - The semi-empirical and compact model approaches (Paperback, Previously published in hardcover)

IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate optimization problem, or a mixture? Optimization algorithms are attractive from a system perspective of course, but what about low-voltage low-power circuits, requiring a more physical approach? The connections amid transistor physics and circuits are intricate and their interactions not always easy to describe in terms of existing software packages. The gm/ID synthesis methodology is adapted to CMOS analog circuits for the transconductance over drain current ratio combines most of the ingredients needed in order to determine transistors sizes and DC currents.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Series:	Analog Circuits and Signal Processing
Release date:	May 2012
First published:	2010
Authors:	Paul Jespers
Dimensions:	235 x 155 x 10mm (L x W x T)
Format:	Paperback
Pages:	171
Edition:	Previously published in hardcover
ISBN-13:	978-1-4614-2505-2
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Electronic devices & materials > Semi-conductors & super-conductors Promotions
LSN:	1-4614-2505-0
Barcode:	9781461425052

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