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Books > Professional & Technical > Electronics & communications engineering > Electronics engineering
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Layout Minimization of CMOS Cells (Hardcover, 1992 ed.)
Loot Price: R2,977
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Layout Minimization of CMOS Cells (Hardcover, 1992 ed.)
Series: The Springer International Series in Engineering and Computer Science, 160
Expected to ship within 10 - 15 working days
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The layout of an integrated circuit (lC) is the process of
assigning geometric shape, size and position to the components
(transistors and connections) used in its fabrication. Since the
number of components in modem ICs is enormous, computer
aided-design (CAD) programs are required to automate the difficult
layout process. Prior CAD methods are inexact or limited in scope,
and produce layouts whose area, and consequently manufacturing
costs, are larger than necessary. This book addresses the problem
of minimizing exactly the layout area of an important class of
basic IC structures called CMOS cells. First, we precisely define
the possible goals in area minimization for such cells, namely
width and height minimization, with allowance for area-reducing
reordering of transistors. We reformulate the layout problem in
terms of a graph model and develop new graph-theoretic concepts
that completely characterize the fundamental area minimization
problems for series-parallel and nonseries-parallel circuits. These
concepts lead to practical algorithms that solve all the basic
layout minimization problems exactly, both for a single cell and
for a one-dimensional array of such cells. Although a few of these
layout problems have been solved or partially solved previously, we
present here the first complete solutions to all the problems of
interest."
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