A Primer on Compression in the Memory Hierarchy (Paperback)

This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardware compression algorithms to cache, memory, and the memory/cache link. There are many non-trivial challenges that must be addressed to make data compression work well in this context. First, since compressed data must be decompressed before it can be accessed, decompression latency ends up on the critical memory access path. This imposes a significant constraint on the choice of compression algorithms. Second, while conventional memory systems store fixed-size entities like data types, cache blocks, and memory pages, these entities will suddenly vary in size in a memory system that employs compression. Dealing with variable size entities in a memory system using compression has a significant impact on the way caches are organized and how to manage the resources in main memory. We systematically discuss solutions in the open literature to these problems. Chapter 2 provides the foundations of data compression by first introducing the fundamental concept of value locality. We then introduce a taxonomy of compression algorithms and show how previously proposed algorithms fit within that logical framework. Chapter 3 discusses the different ways that cache memory systems can employ compression, focusing on the trade-offs between latency, capacity, and complexity of alternative ways to compact compressed cache blocks. Chapter 4 discusses issues in applying data compression to main memory and Chapter 5 covers techniques for compressing data on the cache-to-memory links. This book should help a skilled memory system designer understand the fundamental challenges in applying compression to the memory hierarchy and introduce him/her to the state-of-the-art techniques in addressing them.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Series:	Synthesis Lectures on Computer Architecture
Release date:	December 2015
First published:	2016
Authors:	Somayeh Sardashti • Angelos Arelakis • Per Stenstroem • David A. Wood
Dimensions:	235 x 191mm (L x W)
Format:	Paperback
Pages:	70
ISBN-13:	978-3-03-100623-4
Languages:	English
Subtitles:	English
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Promotions
LSN:	3-03-100623-2
Barcode:	9783031006234

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