This book provides an overview of automatic test pattern
generation (ATPG) and introduces novel techniques to complement
classical ATPG, based on Boolean Satisfiability (SAT). A fast and
highly fault efficient SAT-based ATPG framework is presented which
is also able to generate high-quality delay tests such as robust
path delay tests, as well as tests with long propagation paths to
detect small delay defects.
The aim of the techniques and methodologies presented in this
book is to improve SAT-based ATPG, in order to make it applicable
in industrial practice. Readers will learn to improve the
performance and robustness of the overall test generation process,
so that the ATPG algorithm reliably will generate test patterns for
most targeted faults in acceptable run time to meet the high fault
coverage demands of industry. The techniques and improvements
presented in this book provide the following advantages:
Provides a comprehensive introduction to test generation and
Boolean Satisfiability (SAT);Describes a highly fault efficient
SAT-based ATPG framework; Introduces circuit-oriented SAT solving
techniques, which make use of structural information and are able
to accelerate the search process significantly;Provides SAT
formulations for the prevalent delay faults models, in addition to
the classical stuck-at fault model;Includes an industrial
perspective on the state-of-the-art in the testing, along with SAT;
two topics typically distinguished from each other.
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