One of the keys to success in the IC industry is getting a new
product to market in a timely fashion and being able to produce
that product with sufficient yield to be profitable. There are two
ways to increase yield: by improving the control of the
manufacturing process and by designing the process and the circuits
in such a way as to minimize the effect of the inherent variations
of the process on performance. The latter is typically referred to
as "design for manufacture" or "statistical design." As device
sizes continue to shrink, the effects of the inherent fluctuations
in the IC fabrication process will have an even more obvious effect
on circuit performance. And design for manufacture will increase in
importance. We have been working in the area of statistically based
computer aided design for more than 13 years. During the last
decade we have been working with each other, and individually with
our students, to develop methods and CAD tools that can be used to
improve yield during the design and manufacturing phases of IC
realization. This effort has resulted in a large number of
publications that have appeared in a variety of journals and
conference proceedings. Thus our motivation in writing this book is
to put, in one place, a description of our approach to IC yield
enhancement. While the work that is contained in this book has
appeared in the open literature, we have attempted to use a
consistent notation throughout this book.
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