SystemVerilog for Hardware Description - RTL Design and Verification (Hardcover, 1st ed. 2020)

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.

General

Imprint:	Springer Verlag, Singapore
Country of origin:	Singapore
Release date:	June 2020
First published:	2020
Authors:	Vaibbhav Taraate
Dimensions:	235 x 155mm (L x W)
Format:	Hardcover
Pages:	252
Edition:	1st ed. 2020
ISBN-13:	978-981-15-4404-0
Categories:	Books > Computing & IT > General theory of computing > Data structures Books > Computing & IT > Computer programming > Algorithms & procedures Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN:	981-15-4404-2
Barcode:	9789811544040

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