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Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach (Hardcover, 1st ed. 2023)
Loot Price: R5,220
Discovery Miles 52 200
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Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach (Hardcover, 1st ed. 2023)
Expected to ship within 12 - 17 working days
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With the end of Dennard scaling and Moore's law, IC chips,
especially large-scale ones, now face more reliability challenges,
and reliability has become one of the mainstay merits of VLSI
designs. In this context, this book presents a built-in on-chip
fault-tolerant computing paradigm that seeks to combine fault
detection, fault diagnosis, and error recovery in large-scale VLSI
design in a unified manner so as to minimize resource overhead and
performance penalties. Following this computing paradigm, we
propose a holistic solution based on three key components:
self-test, self-diagnosis and self-repair, or "3S" for short. We
then explore the use of 3S for general IC designs, general-purpose
processors, network-on-chip (NoC) and deep learning accelerators,
and present prototypes to demonstrate how 3S responds to in-field
silicon degradation and recovery under various runtime faults
caused by aging, process variations, or radical particles.
Moreover, we demonstrate that 3S not only offers a powerful
backbone for various on-chip fault-tolerant designs and
implementations, but also has farther-reaching implications such as
maintaining graceful performance degradation, mitigating the impact
of verification blind spots, and improving chip yield. This book is
the outcome of extensive fault-tolerant computing research pursued
at the State Key Lab of Processors, Institute of Computing
Technology, Chinese Academy of Sciences over the past decade. The
proposed built-in on-chip fault-tolerant computing paradigm has
been verified in a broad range of scenarios, from small processors
in satellite computers to large processors in HPCs. Hopefully, it
will provide an alternative yet effective solution to the growing
reliability challenges for large-scale VLSI designs.
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