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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Hardcover, 1st ed. 2018) Loot Price: R3,362
Discovery Miles 33 620
Repayment Terms: R315 pm x 12*
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Hardcover, 1st ed. 2018): Zheng Wang,...

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Hardcover, 1st ed. 2018)

Zheng Wang, Anupam Chattopadhyay

Series: Computer Architecture and Design Methodologies

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Loot Price R3,362 Discovery Miles 33 620 | Repayment Terms: R315 pm x 12*

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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

General

Imprint: Springer Verlag, Singapore
Country of origin: Singapore
Series: Computer Architecture and Design Methodologies
Release date: July 2017
First published: 2018
Authors: Zheng Wang • Anupam Chattopadhyay
Dimensions: 235 x 155mm (L x W)
Format: Hardcover
Pages: 197
Edition: 1st ed. 2018
ISBN-13: 978-981-10-1072-9
Categories: Books > Computing & IT > General theory of computing > Systems analysis & design
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN: 981-10-1072-2
Barcode: 9789811010729

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