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In the early days of VLSI, the design of the power distribution for
an integrated cir cuit was rather simple. Power distribution --the
design of the geometric topology for the network of wires that
connect the various power supplies, the widths of the indi vidual
segments for each of these wires, the number and location of the
power I/O pins around the periphery of the chip --was simple
because the chips were simpler. Few available wiring layers forced
floorplans that allowed simple, planar (non-over lapping) power
networks. Lower speeds and circuit density made the choice of the
wire widths easier: we made them just fat enough to avoid resistive
voltage drops due to switching currents in the supply network. And
we just didn't need enormous num bers of power and ground pins on
the package for the chips to work. It's not so simple any more.
Increased integration has forced us to focus on reliability
concerns such as metal elec tromigration, which affects wire sizing
decisions in the power network. Extra metal layers have allowed
more flexibility in the topological layout of the power networks."
The move to higher levels of integration has increased the fraction
of application-specific integrated circuit (ASIC) designs
containing both analog and digital circuits. While the die area for
the analog portion of these chips is modest, the design time is
often significant. This has motivated the development of automated
analog physical design tools for cell-level place-and-route and
system-level signal-integrity-routing. To date, there is no tool
that has specifically addressed the critical design task of
synthesizing the power distribution for the analog portion of an
analog or mixed-signal ASIC. Synthesis of Power Distribution to
Manage Signal Integrity in Mixed-Signal ICs describes algorithms
for analog power distribution synthesis and demonstrates their
effectiveness. Existing digital power bus synthesis algorithms have
failed to address critical concerns for analog circuitry, thus
yielding unacceptable results. These tools synthesize only the bus
component of power distribution networks and only consider
simplified DC aspects of macros and busses. Readers of the
companion book in this series, Simulation Techniques and Solutions
for Mixed-Signal Coupling in Integrated Circuits (Kluwer Academic
Publishers), already recognize the inadequacy of this simplified
view of the noise and power distribution problem in mixed-signal
integrated circuits. Synthesis of Power Distribution to Manage
Signal Integrity in Mixed-Signal ICs addresses power distribution
synthesis for mixed-signal integrated circuits. Several key
challenges in power distribution design are identified and
automated methods to overcome them are described. This book
presents a new formulation for the analog powerdistribution
synthesis problem which synthesizes both the power busses power I/O
cell assignment by evaluating DC, AC, and transient interaction
between the macros, busses, chip substrate, and package.
Furthermore, algorithms are introduced which simultaneously
optimize power I/O cell assignment, macro cell substrate coupling,
power bus topology selection and power bus sizing. Synthesis of
Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
will be of interest to CAD designers and researchers specializing
in physical design, modelling and circuit synthesis.
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