This book contains extended versions of the best papers presented at the 15th International Conference on Information and Communication Technologies in Education, Research, and Industrial Applications, ICTERI 2019, held in Kherson, Ukraine, in June 2019. The 19 revised full papers included in this volume were carefully reviewed and selected from 416 initial submissions. The papers are organized in the following topical sections: advances in ICT and IS research; ICT in teaching, learning, and education management; applications of ICT in industrial and public practice.

Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.

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