In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

This book explores break-through approaches to tackling and mitigating the well-known problems of compiler optimization using design space exploration and machine learning techniques. It demonstrates that not all the optimization passes are suitable for use within an optimization sequence and that, in fact, many of the available passes tend to counteract one another. After providing a comprehensive survey of currently available methodologies, including many experimental comparisons with state-of-the-art compiler frameworks, the book describes new approaches to solving the problem of selecting the best compiler optimizations and the phase-ordering problem, allowing readers to overcome the enormous complexity of choosing the right order of optimizations for each code segment in an application. As such, the book offers a valuable resource for a broad readership, including researchers interested in Computer Architecture, Electronic Design Automation and Machine Learning, as well as computer architects and compiler developers.

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.