This volume starts with a description of the metrics and benchmarks used to design energy-efficient microprocessor systems, followed by energy-efficient methodologies for the architecture and circuit design, DC-DC conversion, energy-efficient software and system integration.

Low-Power CMOS Wireless Communications: A Wideband CDMA System Design focuses on the issues behind the development of a high-bandwidth, silicon complementary metal-oxide silicon (CMOS) low-power transceiver system for mobile RF wireless data communications. In the design of any RF communications system, three distinct factors must be considered: the propagation environment in question, the multiplexing and modulation of user data streams, and the complexity of hardware required to implement the desired link. None of these can be allowed to dominate. Coupling between system design and implementation is the key to simultaneously achieving high bandwidth and low power and is emphasized throughout the book. The material presented in Low-Power CMOS Wireless Communications: A Wideband CDMA System Design is the result of broadband wireless systems research done at the University of California, Berkeley. The wireless development was motivated by a much larger collaborative effort known as the Infopad Project, which was centered on developing a mobile information terminal for multimedia content - a wireless network computer'. The desire for mobility, combined with the need to support potentially hundreds of users simultaneously accessing full-motion digital video, demanded a wireless solution that was of far lower power and higher data rate than could be provided by existing systems. That solution is the topic of this book: a case study of not only wireless systems designs, but also the implementation of such a link, down to the analog and digital circuit level.

Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.

A silicon compiler is a software system which can automatically generate an integrated circuit from a user's specification. Anatomy of a Silicon Compiler examines one such compiler in detail, covering the basic framework and design entry, the actual algorithms and libraries which are used, the approach to verification and testing, behavioral synthesis tools and several applications which demonstrate the system's capabilities.

A silicon compiler is a software system which can automatically generate an integrated circuit from a user's specification. Anatomy of a Silicon Compiler examines one such compiler in detail, covering the basic framework and design entry, the actual algorithms and libraries which are used, the approach to verification and testing, behavioral synthesis tools and several applications which demonstrate the system's capabilities.

Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible. The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.

Low-Power CMOS Wireless Communications: A Wideband CDMA System Design focuses on the issues behind the development of a high-bandwidth, silicon complementary metal-oxide silicon (CMOS) low-power transceiver system for mobile RF wireless data communications. In the design of any RF communications system, three distinct factors must be considered: the propagation environment in question, the multiplexing and modulation of user data streams, and the complexity of hardware required to implement the desired link. None of these can be allowed to dominate. Coupling between system design and implementation is the key to simultaneously achieving high bandwidth and low power and is emphasized throughout the book. The material presented in Low-Power CMOS Wireless Communications: A Wideband CDMA System Design is the result of broadband wireless systems research done at the University of California, Berkeley. The wireless development was motivated by a much larger collaborative effort known as the Infopad Project, which was centered on developing a mobile information terminal for multimedia content - a wireless `network computer'. The desire for mobility, combined with the need to support potentially hundreds of users simultaneously accessing full-motion digital video, demanded a wireless solution that was of far lower power and higher data rate than could be provided by existing systems. That solution is the topic of this book: a case study of not only wireless systems designs, but also the implementation of such a link, down to the analog and digital circuit level.

This volume starts with a description of the metrics and benchmarks used to design energy-efficient microprocessor systems, followed by energy-efficient methodologies for the architecture and circuit design, DC-DC conversion, energy-efficient software and system integration.