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Routing Congestion in VLSI Circuits - Estimation and Optimization (Hardcover, 2007 ed.): Prashant Saxena, Rupesh S Shelar,... Routing Congestion in VLSI Circuits - Estimation and Optimization (Hardcover, 2007 ed.)
Prashant Saxena, Rupesh S Shelar, Sachin Sapatnekar
R4,497 Discovery Miles 44 970 Ships in 10 - 15 working days

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

Routing Congestion in VLSI Circuits - Estimation and Optimization (Paperback, Softcover reprint of hardcover 1st ed. 2007):... Routing Congestion in VLSI Circuits - Estimation and Optimization (Paperback, Softcover reprint of hardcover 1st ed. 2007)
Prashant Saxena, Rupesh S Shelar, Sachin Sapatnekar
R3,119 Discovery Miles 31 190 Ships in 10 - 15 working days

This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

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