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Routing Congestion in VLSI Circuits - Estimation and Optimization (Hardcover, 2007 ed.) Loot Price: R4,497
Discovery Miles 44 970
Routing Congestion in VLSI Circuits - Estimation and Optimization (Hardcover, 2007 ed.): Prashant Saxena, Rupesh S Shelar,...

Routing Congestion in VLSI Circuits - Estimation and Optimization (Hardcover, 2007 ed.)

Prashant Saxena, Rupesh S Shelar, Sachin Sapatnekar

Series: Integrated Circuits and Systems

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Loot Price R4,497 Discovery Miles 44 970 | Repayment Terms: R421 pm x 12*

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This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Series: Integrated Circuits and Systems
Release date: April 2007
First published: 2007
Authors: Prashant Saxena • Rupesh S Shelar • Sachin Sapatnekar
Dimensions: 235 x 155 x 15mm (L x W x T)
Format: Hardcover
Pages: 250
Edition: 2007 ed.
ISBN-13: 978-0-387-30037-5
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Electronic devices & materials > General
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LSN: 0-387-30037-6
Barcode: 9780387300375

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