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Wafer Level 3-D ICs Process Technology (Hardcover, 2009 ed.) Loot Price: R4,278
Discovery Miles 42 780
Repayment Terms: R401 pm x 12*
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Wafer Level 3-D ICs Process Technology (Hardcover, 2009 ed.): Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif

Wafer Level 3-D ICs Process Technology (Hardcover, 2009 ed.)

Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif

Series: Integrated Circuits and Systems

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List price R5,691 Loot Price R4,278 Discovery Miles 42 780 | Repayment Terms: R401 pm x 12* You Save R1,413 (25%)

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Wafer Level 3-D ICs Process Technology (Hardcover, 2009 ed.): Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif
Wafer Level 3-D ICs Process Technology
R4,278
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This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Series: Integrated Circuits and Systems
Release date: September 2008
First published: November 2008
Editors: Chuan Seng Tan • Ronald J. Gutmann • L. Rafael Reif
Dimensions: 235 x 155 x 23mm (L x W x T)
Format: Hardcover
Pages: 410
Edition: 2009 ed.
ISBN-13: 978-0-387-76532-7
Categories: Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General
LSN: 0-387-76532-8
Barcode: 9780387765327

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