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Metric Driven Design Verification - An Engineer's and Executive's Guide to First Pass Success (Paperback, Softcover reprint of hardcover 1st ed. 2007)
Loot Price: R3,885
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Metric Driven Design Verification - An Engineer's and Executive's Guide to First Pass Success (Paperback, Softcover reprint of hardcover 1st ed. 2007)
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Verification Projects: Planning to Closure addresses the
challenges of functional verification in the digital semiconductor
market today. It presents best practices by alternately looking at
the verification problem as a complete system, and expounding on
the best practices for executing with the myriad of available
verification technologies. As a result, the reader gains not only a
sufficient knowledge to use each technology intelligently, but more
importantly, knowledge of when each technology can be used most
effectively, and how to combine the various technologies to provide
the best verification solution for their project.
All of this information is conveyed within the framework of the
leading edge plan to closure methodology. This methodology conveys
three important messages:
- Effective planning of the verification effort using
well-defined measurable objectives to gauge the project status as
it proceeds. It is shown that this planning is valuable for
tracking and reacting to project status, (of more importance, and
far more emphasized in the management book). Furthermore, and, more
importantly here, we show that planning helps ensure that the right
verification environment is built the first time using optimal tool
and resource selections. We also show that appropriate planning
significantly reduces the amount of effort put into verification,
(currently estimated to be about 70% of the complete project
effort).
- By using appropriate horizontal re-use methodologies, project
quality, productivity, and predictability can be greatly enhanced.
These methodologies include how to best design and package
verification intellectual property so that it can be re-used from
project to project.
- By using appropriate vertical re-use methodologies, project
quality, productivity, and predictability can be greatly enhanced.
These methodologies are discussed including how to best design and
package verification intellectual property so that projects can
benefit by effectively using each level of verification as building
blocks for successive levels throughout the project. For example,
how to best re-use of block level environments at the chip level,
how to best architect environments so that they can be easily used
in both simulators and emulators, and how to design environments so
that they can easily facilitate system level modeling, RTL
verification and software verification.
It is important to note that while this book will touch on all
available verification technologies, it is not meant to be an
in-depth training manual on any one technology. That level of
material has been well covered in other books. The intent of this
book is to teach the user a fundamental understanding of each
technology, teach the user how to best employ each technology and
teach the user how to execute most effectively with these
technologies using a plan to closure methodology.
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