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Books > Computing & IT > General theory of computing
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Advanced ASIC Chip Synthesis - Using Synopsys Design Compiler and PrimeTime (Hardcover)
Loot Price: R2,598
Discovery Miles 25 980
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Advanced ASIC Chip Synthesis - Using Synopsys Design Compiler and PrimeTime (Hardcover)
Expected to ship within 12 - 19 working days
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This text describes the advanced concepts and techniques used for
ASIC chip synthesis, formal verification and static timing
analysis, using the Synopsys suite of tools. In addition, the
entire ASIC design flow methodology targeted for VDSM
(Very-Deep-Sub-Micron) technologies is covered in detail. The
emphasis of this book is on real-time application of Synopsys tools
used to combat various problems seen at VDSM geometries. Readers
are exposed to an effective design methodology for handling
complex, sub-micron ASIC designs. Significance is placed on HDL
coding styles, synthesis and optimization, dynamic simulation,
formal verification, DFT scan insertion, links to layout, and
static timing analysis. At each step, problems related to each
phase of the design flow are identified, with solutions and
work-arounds described in detail. In addition, crucial issues
related to layout, which includes clock tree synthesis and back-end
integration (links to layout) are also discussed at length. The
book is intended for anyone who is involved in the ASIC design
methodology, starting from RTL synthesis to final tape-out. Target
audiences for this book are practicing ASIC design engineers and
graduate students undertaking advanced courses in ASIC chip design
and DFT techniques.
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