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Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended (Paperback, 1st ed. 2020)
Loot Price: R2,927
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Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended (Paperback, 1st ed. 2020)
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This book presents MOSFET-based current mode logic (CML)
topologies, which increase the speed, and lower the transistor
count, supply voltage and power consumption. The improved
topologies modify the conventional PDN, load, and the current
source sections of the basic CML gates. Electronic system
implementation involves embedding digital and analog circuits on a
single die shifting towards mixed-mode circuit design. The
high-resolution, low-power and low-voltage analog circuits are
combined with high-frequency complex digital circuits, and the
conventional static CMOS logic generates large current spikes
during the switching (also referred to as digital switching noise),
which degrade the resolution of the sensitive analog circuits via
supply line and substrate coupling. This problem is exacerbated
further with scaling down of CMOS technology due to higher
integration levels and operating frequencies. In the literature,
several methods are described to reduce the propagation of the
digital switching noise. However, in high-resolution applications,
these methods are not sufficient. The conventional CMOS static
logic is no longer an effective solution, and therefore an
alternative with reduced current spikes or that draws a constant
supply current must be selected. The current mode logic (CML)
topology, with its unique property of requiring constant supply
current, is a promising alternative to the conventional CMOS static
logic.
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