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It is widely acknowledged that the cost of validation and testing
comprises a s- nificant percentage of the overall development costs
for electronic systems today, and is expected to escalate sharply
in the future. Many studies have shown that up to 70% of the design
development time and resources are spent on functional
verification. Functional errors manifest themselves very early in
the design flow, and unless they are detected up front, they can
result in severe consequence- both financially and from a safety
viewpoint. Indeed, several recent instances of high-profile
functional errors (e. g. , the Pentium FDIV bug) have resulted in -
creased attention paid to verifying the functional correctness of
designs. Recent efforts have proposed augmenting the traditional
RTL simulation-based validation methodology with formal techniques
in an attempt to uncover hard-to-find c- ner cases, with the goal
of trying to reach RTL functional verification closure. However,
what is often not highlighted is the fact that in spite of the
tremendous time and effort put into such efforts at the RTL and
lower levels of abstraction, the complexity of contemporary
embedded systems makes it difficult to guarantee functional
correctness at the system level under all possible operational
scenarios. The problem is exacerbated in current System-on-Chip
(SOC) design meth- ologies that employ Intellectual Property (IP)
blocks composed of processor cores, coprocessors, and memory
subsystems. Functional verification becomes one of the major
bottlenecks in the design of such systems.
Rapid advances in microelectronic integration and the advent of
Systems-on-Chip have fueled the need for high-level synthesis,
i.e., an automated approach to the synthesis of hardware from
behavioral descriptions.
SPARK: A Parallelizing Approach to the High - Level Synthesis of
Digital Circuits presents a novel approach to the high-level
synthesis of digital circuits -- that of parallelizing high-level
synthesis (PHLS). This approach uses aggressive code parallelizing
and code motion techniques to discover circuit optimization
opportunities beyond what is possible with traditional high-level
synthesis. This PHLS approach addresses the problems of the poor
quality of synthesis results and the lack of controllability over
the transformations applied during the high-level synthesis of
system descriptions with complex control flows, that is, with
nested conditionals and loops.
Also described are speculative code motion techniques and dynamic
compiler transformations that optimize the circuit quality in terms
of cycle time, circuit size and interconnect costs. We describe the
SPARK parallelizing high-level synthesis framework in which we have
implemented these techniques and demonstrate the utility of SPARK's
PHLS approach using designs derived from multimedia and image
processing applications. We also present a case study of an
instruction length decoder derived from the Intel Pentium-class of
microprocessors. This case study serves as an example of a typical
microprocessor functional block with complex control flow and
demonstrates how our techniques are useful for such designs.
SPARK: A Parallelizing Approach to the High - Level Synthesis of
Digital Circuits is targeted mainly to embedded system designers
and researchers. This includes people working on design and design
automation. The book is useful for researchers and design
automation engineers who wish to understand how the main problems
hindering the adoption of high-level synthesis among designers.
Memory Issues in Embedded Systems-On-Chip: Optimizations and
Explorations is designed for different groups in the embedded
systems-on-chip arena. First, it is designed for researchers and
graduate students who wish to understand the research issues
involved in memory system optimization and exploration for embedded
systems-on-chip. Second, it is intended for designers of embedded
systems who are migrating from a traditional micro-controllers
centered, board-based design methodology to newer design
methodologies using IP blocks for processor-core-based embedded
systems-on-chip. Also, since Memory Issues in Embedded
Systems-on-Chip: Optimization and Explorations illustrates a
methodology for optimizing and exploring the memory configuration
of embedded systems-on-chip, it is intended for managers and system
designers who may be interested in the emerging capabilities of
embedded systems-on-chip design methodologies for memory-intensive
applications.
Research on high-level synthesis started over twenty years ago, but
lower-level tools were not available to seriously support the
insertion of high-level synthesis into the mainstream design
methodology. Since then, substantial progress has been made in
formulating and understanding the basic concepts in high-level
synthesis. Although many open problems remain, high-level synthesis
has matured. High-Level Synthesis: Introduction to Chip and System
Design presents a summary of the basic concepts and results and
defines the remaining open problems. This is the first textbook on
high-level synthesis and includes the basic concepts, the main
algorithms used in high-level synthesis and a discussion of the
requirements and essential issues for high-level synthesis systems
and environments. A reference text like this will allow the
high-level synthesis community to grow and prosper in the future.
Memory Architecture Exploration for Programmable Embedded Systems
addresses efficient exploration of alternative memory
architectures, assisted by a "compiler-in-the-loop" that allows
effective matching of the target application to the
processor-memory architecture. This new approach for memory
architecture exploration replaces the traditional black-box view of
the memory system and allows for aggressive co-optimization of the
programmable processor together with a customized memory system.
The book concludes with a set of experiments demonstrating the
utility of this exploration approach. The authors perform
architecture and compiler exploration for a set of large, real-life
benchmarks, uncovering promising memory configurations from
different perspectives, such as cost, performance and power.
It is widely acknowledged that the cost of validation and testing
comprises a s- nificant percentage of the overall development costs
for electronic systems today, and is expected to escalate sharply
in the future. Many studies have shown that up to 70% of the design
development time and resources are spent on functional
verification. Functional errors manifest themselves very early in
the design flow, and unless they are detected up front, they can
result in severe consequence- both financially and from a safety
viewpoint. Indeed, several recent instances of high-profile
functional errors (e. g. , the Pentium FDIV bug) have resulted in -
creased attention paid to verifying the functional correctness of
designs. Recent efforts have proposed augmenting the traditional
RTL simulation-based validation methodology with formal techniques
in an attempt to uncover hard-to-find c- ner cases, with the goal
of trying to reach RTL functional verification closure. However,
what is often not highlighted is the fact that in spite of the
tremendous time and effort put into such efforts at the RTL and
lower levels of abstraction, the complexity of contemporary
embedded systems makes it difficult to guarantee functional
correctness at the system level under all possible operational
scenarios. The problem is exacerbated in current System-on-Chip
(SOC) design meth- ologies that employ Intellectual Property (IP)
blocks composed of processor cores, coprocessors, and memory
subsystems. Functional verification becomes one of the major
bottlenecks in the design of such systems.
Rapid advances in microelectronic integration and the advent of
Systems-on-Chip have fueled the need for high-level synthesis,
i.e., an automated approach to the synthesis of hardware from
behavioral descriptions.
SPARK: A Parallelizing Approach to the High - Level Synthesis of
Digital Circuits presents a novel approach to the high-level
synthesis of digital circuits -- that of parallelizing high-level
synthesis (PHLS). This approach uses aggressive code parallelizing
and code motion techniques to discover circuit optimization
opportunities beyond what is possible with traditional high-level
synthesis. This PHLS approach addresses the problems of the poor
quality of synthesis results and the lack of controllability over
the transformations applied during the high-level synthesis of
system descriptions with complex control flows, that is, with
nested conditionals and loops.
Also described are speculative code motion techniques and dynamic
compiler transformations that optimize the circuit quality in terms
of cycle time, circuit size and interconnect costs. We describe the
SPARK parallelizing high-level synthesis framework in which we have
implemented these techniques and demonstrate the utility of SPARK's
PHLS approach using designs derived from multimedia and image
processing applications. We also present a case study of an
instruction length decoder derived from the Intel Pentium-class of
microprocessors. This case study serves as an example of a typical
microprocessor functional block with complex control flow and
demonstrates how our techniques are useful for such designs.
SPARK: A Parallelizing Approach to the High - Level Synthesis of
Digital Circuits is targeted mainlyto embedded system designers and
researchers. This includes people working on design and design
automation. The book is useful for researchers and design
automation engineers who wish to understand how the main problems
hindering the adoption of high-level synthesis among designers.
Memory Architecture Exploration for Programmable Embedded Systems
addresses efficient exploration of alternative memory
architectures, assisted by a "compiler-in-the-loop" that allows
effective matching of the target application to the
processor-memory architecture. This new approach for memory
architecture exploration replaces the traditional black-box view of
the memory system and allows for aggressive co-optimization of the
programmable processor together with a customized memory system.
The book concludes with a set of experiments demonstrating the
utility of this exploration approach. The authors perform
architecture and compiler exploration for a set of large, real-life
benchmarks, uncovering promising memory configurations from
different perspectives, such as cost, performance and power.
Memory Issues in Embedded Systems-On-Chip: Optimizations and
Explorations is designed for different groups in the embedded
systems-on-chip arena. First, it is designed for researchers and
graduate students who wish to understand the research issues
involved in memory system optimization and exploration for embedded
systems-on-chip. Second, it is intended for designers of embedded
systems who are migrating from a traditional micro-controllers
centered, board-based design methodology to newer design
methodologies using IP blocks for processor-core-based embedded
systems-on-chip. Also, since Memory Issues in Embedded
Systems-on-Chip: Optimization and Explorations illustrates a
methodology for optimizing and exploring the memory configuration
of embedded systems-on-chip, it is intended for managers and system
designers who may be interested in the emerging capabilities of
embedded systems-on-chip design methodologies for memory-intensive
applications.
Research on high-level synthesis started over twenty years ago, but
lower-level tools were not available to seriously support the
insertion of high-level synthesis into the mainstream design
methodology. Since then, substantial progress has been made in
formulating and understanding the basic concepts in high-level
synthesis. Although many open problems remain, high-level synthesis
has matured. High-Level Synthesis: Introduction to Chip and System
Design presents a summary of the basic concepts and results and
defines the remaining open problems. This is the first textbook on
high-level synthesis and includes the basic concepts, the main
algorithms used in high-level synthesis and a discussion of the
requirements and essential issues for high-level synthesis systems
and environments. A reference text like this will allow the
high-level synthesis community to grow and prosper in the future.
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