This reference text covers a wide spectrum for designing robust embedded memory and peripheral circuitry. It will serve as a useful text for senior undergraduate, graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discusses low power design methodologies for SRAM. Covers radiation hardened SRAM design for aerospace applications. Focusses on various reliability issues which are faced by sub-micron technologies. Exhibits more stable memory topologies. Nanoscale technologies unveiled significant challenges to the design of energy efficient and reliable SRAMs. This reference text investigates the impact of process variation, leakage, aging, soft errors and related reliability issues in embedded memory and periphery circuitry. The text adopts a unique way to explain SRAM bitcell, array design and analysis of its design parameters to meet the sub-nano-regime challenges for CMOS devices. It comprehensively covers low power design methodologies for SRAM, exhibits more stable memory topologies, and radiation hardened SRAM design for aerospace applications. Every chapter includes glossary, highlights, question bank, and problems. The text will serve as a useful text for senior undergraduate, graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discussing compressively study of variability induced failure mechanism in sense amplifiers and power, delay and read yield trade-offs, this reference text will serve as a useful text for senior undergraduate, graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. It covers development of robust SRAMs, well suited for low-power multi-core processors for wireless sensors node, battery-operated portable devices, personal healthcare assistants and smart IoT applications.

This book constitutes the refereed proceedings of the 23st International Symposium on VLSI Design and Test, VDAT 2019, held in Indore, India, in July 2019. The 63 full papers were carefully reviewed and selected from 199 submissions. The papers are organized in topical sections named: analog and mixed signal design; computing architecture and security; hardware design and optimization; low power VLSI and memory design; device modelling; and hardware implementation.