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From Contamination to Defects, Faults and Yield Loss - Simulation and Applications (Paperback, Softcover reprint of the original 1st ed. 1996) Loot Price: R2,838
Discovery Miles 28 380
From Contamination to Defects, Faults and Yield Loss - Simulation and Applications (Paperback, Softcover reprint of the...

From Contamination to Defects, Faults and Yield Loss - Simulation and Applications (Paperback, Softcover reprint of the original 1st ed. 1996)

Jitendra B. Khare, Wojciech Maly

Series: Frontiers in Electronic Testing, 5

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Loot Price R2,838 Discovery Miles 28 380 | Repayment Terms: R266 pm x 12*

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Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Series: Frontiers in Electronic Testing, 5
Release date: September 2011
First published: 1996
Authors: Jitendra B. Khare • Wojciech Maly
Dimensions: 235 x 155 x 9mm (L x W x T)
Format: Paperback
Pages: 150
Edition: Softcover reprint of the original 1st ed. 1996
ISBN-13: 978-1-4612-8595-3
Categories: Books > Professional & Technical > Technology: general issues > Technical design > Computer aided design (CAD)
Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
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LSN: 1-4612-8595-X
Barcode: 9781461285953

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