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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design
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A Pipelined Multi-core MIPS Machine - Hardware Implementation and Correctness Proof (Paperback, 2014 ed.)
Loot Price: R2,462
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A Pipelined Multi-core MIPS Machine - Hardware Implementation and Correctness Proof (Paperback, 2014 ed.)
Series: Lecture Notes in Computer Science, 9000
Expected to ship within 10 - 15 working days
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This monograph is based on the third author's lectures on computer
architecture, given in the summer semester 2013 at Saarland
University, Germany. It contains a gate level construction of a
multi-core machine with pipelined MIPS processor cores and a
sequentially consistent shared memory. The book contains the first
correctness proofs for both the gate level implementation of a
multi-core processor and also of a cache based sequentially
consistent shared memory. This opens the way to the formal
verification of synthesizable hardware for multi-core processors in
the future. Constructions are in a gate level hardware model and
thus deterministic. In contrast the reference models against which
correctness is shown are nondeterministic. The development of the
additional machinery for these proofs and the correctness proof of
the shared memory at the gate level are the main technical
contributions of this work.
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