A Pipelined Multi-core MIPS Machine - Hardware Implementation and Correctness Proof (Paperback, 2014 ed.)

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Series:	Lecture Notes in Computer Science, 9000
Release date:	November 2014
First published:	2014
Authors:	Mikhail Kovalev • Silvia M. Muller • Wolfgang J. Paul
Dimensions:	235 x 155 x 19mm (L x W x T)
Format:	Paperback
Pages:	352
Edition:	2014 ed.
ISBN-13:	978-3-319-13905-0
Categories:	Books > Computing & IT > General theory of computing > Data structures Books > Computing & IT > Computer programming > Algorithms & procedures Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Books > Computing & IT > Computer programming > Programming languages > General Promotions
LSN:	3-319-13905-3
Barcode:	9783319139050

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