Microelectronic Packaging analyzes the massive impact of electrochemical technologies on various levels of microelectronic packaging. Traditionally, interconnections within a chip were considered outside the realm of packaging technologies, but this book emphasizes the importance of chip wiring as a key aspect of microelectronic packaging, and focuses on electrochemical processing as an enabler of advanced chip metallization. Divided into five parts, the book begins by outlining the basics of electrochemical processing, defining the microelectronic packaging hierarchy, and emphasizing the impact of electrochemical technology on packaging. The second part discusses chip metallization topics including the development of robust barrier layers and alternative metallization materials. Part III explores key aspects of chip-package interconnect technologies, followed by Part IV's analysis of packages, boards, and connectors which covers materials development, technology trends in ceramic packages and multi-chip modules, and electroplated contact materials. Illustrating the importance of processing tools in enabling technology development, the book concludes with chapters on chemical mechanical planarization, electroplating, and wet etching/cleaning tools. Experts from industry, universities, and national laboratories submitted reviews on each of these subjects, capturing the technological advances made in each area. A detailed examination of how packaging responds to the challenges of Moore's law, this book serves as a timely and valuable reference for microelectronic packaging and processing professionals and other industrial technologists.

To address the increasing demands of device scaling, new materials are being introduced into conventional Si CMOS processing at an unprecedented rate. Presentations collected here focus on understanding, from a chemistry and materials perspective, the mechanism of interface formation and defects at interfaces, for both conventional Si and alternative channel (Ge or III-V) systems. Several papers address reliability concerns for high-k/metal gate (basic physical models, charge trapping, etc.), while others cover characterization of the thin films and interfaces which comprise the gate stack. Topics include: advanced Si-based gate stacks; and alternate channel materials.

To address the increasing demands of device scaling, new materials are being introduced into conventional Si CMOS processing at an unprecedented rate. Presentations collected here focus on understanding, from a chemistry and materials perspective, the mechanism of interface formation and defects at interfaces, for both conventional Si and alternative channel (Ge or III-V) systems. Several papers address reliability concerns for high-k/metal gate (basic physical models, charge trapping, etc.), while others cover characterization of the thin films and interfaces which comprise the gate stack. Topics include: advanced Si-based gate stacks; and alternate channel materials.