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Low-Power High-Resolution Analog to Digital Converters - Design, Test and Calibration (Hardcover, Edition.)
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Low-Power High-Resolution Analog to Digital Converters - Design, Test and Calibration (Hardcover, Edition.)
Series: Analog Circuits and Signal Processing
Expected to ship within 12 - 17 working days
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With the fast advancement of CMOS fabrication technology, more and
more signal-processing functions are implemented in the digital
domain for a lower cost, lower power consumption, higher yield, and
higher re-configurability. This has recently generated a great
demand for low-power, low-voltage A/D converters that can be
realized in a mainstream deep-submicron CMOS technology. However,
the discrepancies between lithography wavelengths and circuit
feature sizes are increasing. Lower power supply voltages
significantly reduce noise margins and increase variations in
process, device and design parameters. Consequently, it is steadily
more difficult to control the fabrication process precisely enough
to maintain uniformity. The inherent randomness of materials used
in fabrication at nanoscopic scales means that performance will be
increasingly variable, not only from die-to-die but also within
each individual die. Parametric variability will be compounded by
degradation in nanoscale integrated circuits resulting in
instability of parameters over time, eventually leading to the
development of faults. Process variation cannot be solved by
improving manufacturing tolerances; variability must be reduced by
new device technology or managed by design in order for scaling to
continue. Similarly, within-die performance variation also imposes
new challenges for test methods. In an attempt to address these
issues, Low-Power High-Resolution Analog-to-Digital Converters
specifically focus on: i) improving the power efficiency for the
high-speed, and low spurious spectral A/D conversion performance by
exploring the potential of low-voltage analog design and
calibration techniques, respectively, and ii) development of
circuit techniques and algorithms to enhance testing and debugging
potential to detect errors dynamically, to isolate and confine
faults, and to recover errors continuously. The feasibility of the
described methods has been verified by measurements from the
silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS
technology.
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