Low power, high speed binary multiplier is an essential component
of digital computers. Many architectures of multiplier based on
Booth multiplication and array multiplication algorithms have been
implemented. The array multiplier using Wallace tree structure is
reported to be fastest and requiring minimum hardware. The speed of
a binary multiplier is dominantly determined by the speed of adders
used in the multiplier. This work describes a new 20-transistor low
power high speed hybrid CMOS full adder and a new carry skip adder
suitable for use in multipliers. A new modular design method for
design of n x n multipliers using Vedic algorithm for
multiplication has been proposed. The proposed design method uses
more number of gates than array multiplier using Wallace tree but
offers the advantages of simple and systematic interconnection
scheme and maximum design reuse.
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