Analog and mixed signal integrated systems of today and tomorrow
will be very complex, as they meet the challenge and increased
demand for higher levels of integration in a System on Chip (SoC).
Current and future trends call for pushing system integration to
the highest levels in order to achieve low cost and low power for
large volume products in the consumer and telecom markets, such as
feature-rich handheld battery-operated devices. In todaya (TM)s
analog design environment, a fully integrated CMOS SoC design may
require several silicon spins before it meets all product
specifications and often with relatively low yields. This results
in significant increase in development cost, especially that mask
set costs increase exponentially as feature size scales down.
This book is devoted to the subject of adaptive techniques for
smart analog and mixed signal design whereby fully functional
first-pass silicon is achievable. To our knowledge, this is the
first book devoted to this subject. The techniques described should
lead to quantum improvement in design productivity of complex
analog and mixed signal systems while significantly cutting the
spiraling costs of product development in emerging nanometer
technologies. The underlying principles and design techniques
presented are generic and would certainly apply to CMOS analog and
mixed signal platforms in high volume, low-cost wireless, wire
line, and consumer electronic SoC or chip set solutions.
Adaptive Techniques for Mixed Signal Sytem on Chip discusses the
concept of adaptation in the context of analog and mixed signal
design along with different adaptive architectures used to control
any system parameter. The first part ofthe book gives an overview
of the different elements that are normally used in adaptive
designs including tunable elements as well as voltage, current, and
time references with an emphasis on the circuit design of specific
blocks such as voltage-controlled transconductors, offset
comparators, and a novel technique for accurate implementation of
on chip resistors. While the first part of the book addresses
adaptive techniques at the circuit and block levels, the second
part discusses adaptive equalization architectures employed to
minimize the impact of ISI (Intersymbol Interference) on the
quality of received data in high-speed wire line transceivers. It
presents the implementation of a 125Mbps transceiver operating over
a variable length of Category 5 (CAT-5) Ethernet cable as an
example of adaptive equalizers.
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