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Formal Semantics for VHDL (Paperback, Softcover reprint of the original 1st ed. 1995)
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Formal Semantics for VHDL (Paperback, Softcover reprint of the original 1st ed. 1995)
Series: The Springer International Series in Engineering and Computer Science, 307
Expected to ship within 10 - 15 working days
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It is recognized that formal design and verification methods are an
important requirement for the attainment of high quality system
designs. The field has evolved enormously during the last few
years, resulting in the fact that formal design and verification
methods are nowadays supported by several tools, both commercial
and academic. If different tools and users are to generate and read
the same language then it is necessary that the same semantics is
assigned by them to all constructs and elements of the language.
The current IEEE standard VHDL language reference manual (LRM)
tries to define VHDL as well as possible in a descriptive way,
explaining the semantics in English. But rigor and clarity are very
hard to maintain in a semantics defined in this way, and that has
already given rise to many misconceptions and contradictory
interpretations. Formal Semantics for VHDL is the first book that
puts forward a cohesive set of semantics for the VHDL language. The
chapters describe several semantics each based on a different
underlying formalism: two of them use Petri nets as target
language, and two of them higher order logic. Two use functional
concepts, and finally another uses the concept of evolving
algebras. Formal Semantics for VHDL is essential reading for
researchers in formal methods and can be used as a text for an
advanced course on the subject.
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