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Low Power Methodology Manual - For System-on-Chip Design (Hardcover, 1st ed. 2007. Corr. 2nd printing 2007)
Loot Price: R4,968
Discovery Miles 49 680
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Low Power Methodology Manual - For System-on-Chip Design (Hardcover, 1st ed. 2007. Corr. 2nd printing 2007)
Series: Integrated Circuits and Systems
Expected to ship within 12 - 17 working days
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?Tools alone aren't enough to reduce dynamic and leakage power in
complex chip designs - a well-planned methodology is needed.
Following in the footsteps of the successful Reuse Methodology
Manual (RMM), authors from ARM and Synopsys have written this Low
Power Methodology Manual (LPMM) to describe such] a] low-power
methodology with a practical, step-by-step approach.? Richard
Goering, Software Editor, EE Times ?Excellent compendium of
low-power techniques and guidelines with balanced content spanning
theory and practical implementation. The LPMM is a very welcome
addition to the field of low power SoC implementation that has for
many years operated in a largely ad-hoc fashion.? Sujeeth Joseph,
Chief Architect - Semiconductor and Systems Solutions Unit, Wipro
Technologies ?The LPMM enables broader adoption of aggressive power
management techniques based on extensive experience and silicon
example with real data that every SOC designer can use to meet the
difficulties faced in managing the power issues in deep submicron
designs.? Anil Mankar, Sr VP Worldwide Core Engineering and Chief
Development Officer, Conexant Systems Inc. ?Managing power, at 90nm
and below, introduces significant challenges to design flow. The
LPMM is a timely and immediately useful book that shows how
combination of tools, IP and methodology can be used together to
address power management.? Nick Salter, Head of Chip Integration,
CSR plc.
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