Reconfigurable machines can accelerate many applications by
adapting to their needs through hardware reconfiguration. Partial
reconfiguration allows the reconfiguration of a portion of a chip
while the rest of the chip is still working. Operating system for
partially reconfigurable machines (OS4RC) handles the scheduling
and placement of tasks. Some existing OS4RC models assume no data
exchange channel between IP (Intellectual Property) circuits
residing on a FPGA chip and between an IP circuit and FPGA I/O
pins. Other models assume inter-IP communication channels, but they
do not work well with 2-D partial reconfiguration. And frequently
they are very complicated to design and expensive. To address these
problems, a new chip architecture that can better support inter-IP
and IP-I/O communication is proposed and a corresponding OS4RC
kernel is then specified.The proposed FPGA architecture is based on
an array of clusters of CLBs, with each cluster serving as a
partial reconfiguration unit, and a mesh of segmented buses that
provides inter-IP and IP-I/O communication channels. Features of
the new architecture can reduce the kernel execution times and
enable the runtime scheduling,
General
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